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ZL50062 Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
10
Zarlink Semiconductor Inc.
Pin Description
Pin Name
ZL50064
Package
Coordinates
(256-pin
LQFP)
ZL50062
Package
Coordinates
(256-ball
PBGA)
Description
Device Timing
C8i
37
T10
Master Clock (5V Tolerant Schmitt-Triggered Input). This
pin accepts an 8.192MHz clock. The internal frame boundary
is aligned with the clock falling or rising edge, as controlled by
the C8IPOL bit in the Control Register. Input data on both the
Backplane and Local sides (BSTi0-31 and LSTi0-31) must be
aligned to this clock and the accompanying input frame pulse,
FP8i.
FP8i
43
R11
Frame Pulse Input (5V Tolerant Schmitt-Triggered Input).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin accepts a 122ns-wide
frame pulse. When the FPW bit is HIGH, this pin accepts a
244ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied.
Input data on both the Backplane and Local sides (BSTi0-31
and LSTi0-31) must be aligned to this frame pulse and the
accompanying input clock, C8i.
C8o
41
T11
C8o Output Clock (5V Tolerant Three-state Output). This
pin outputs an 8.192MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP8o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP8o.
FP8o
42
R10
Frame Pulse Output (5V Tolerant Three-state Output).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 122ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
244ns-wide frame pulse. The frame pulse, running at 8kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C8o.
C16o
NA
P10
C16o Output Clock (5V Tolerant Three-state Output). This
pin outputs a 16.384MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP16o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP16o.


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