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ZL50062 Datasheet(PDF) 14 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 14 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
14
Zarlink Semiconductor Inc.
CS
151
A8
Chip Select (5V Tolerant Input). Active LOW input used by
the microprocessor to enable the microprocessor port access.
Note that a minimum of 30ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
DS
157
A6
Data Strobe (5V Tolerant Input). This active LOW input
works in conjunction with CS to enable the microprocessor
port read and write operations. Note that a minimum of 30ns
must separate the de-assertion of DTA (to high) and the
assertion of CS and/or DS to initiate the next access.
R/W
152
A7
Read/Write (5V Tolerant Input). This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
DTA
150
C10
Data Transfer Acknowledgment (5V Tolerant Three-state
Output). This active LOW output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold a
HIGH level. Note that a minimum of 30ns must separate
the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
RESET
148
B11
Device Reset (5V Tolerant Input with Internal Pull-up). This
input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of this
pin also clears the device registers and internal counters.
Refer to Section 7.3 on page 29 for the timing
requirements regarding this reset signal.
JTAG Control Signals
TCK
143
D10
Test Clock (5V Tolerant Input).
Provides the clock to the JTAG test logic.
TMS
147
B12
Test Mode Select (5V Tolerant Input with Internal Pull-up).
JTAG signal that controls the state transitions of the TAP
controller.
TDi
145
C11
Test Serial Data In (5V Tolerant Input with Internal Pull-up).
JTAG serial test instructions and data are shifted in on this pin.
TDo
146
C12
Test Serial Data Out (5V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
Pin Description (continued)
Pin Name
ZL50064
Package
Coordinates
(256-pin
LQFP)
ZL50062
Package
Coordinates
(256-ball
PBGA)
Description


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