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ZL50062 Datasheet(PDF) 15 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 15 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
15
Zarlink Semiconductor Inc.
TRST
144
D11
Test Reset (5V Tolerant Input with Internal Pull-up).
Asynchronously initializes the JTAG TAP controller to the
Test-Logic-Reset state. This pin must be pulsed LOW during
power-up for JTAG testing. This pin must be held LOW for
normal functional operation of the device.
Power and Ground Pins
VDD_IO
7, 20, 34, 48,
67, 87, 99,
109, 120,
134, 153,
173, 189,
198, 211,
224, 243
E5, E6, E11,
E12, F5, F12,
G5, G12, H5,
H12, L5, L12,
M5, M12
Power Supply for Periphery Circuits: +3.3V
VDD_CORE
12, 23, 36,
49, 69, 90,
112, 124,
135, 156,
176, 202,
214, 227, 247
E7, E8, E9,
E10, F6, F11,
J5, J12, K5,
K12, L6, L7,
L10, L11
Power Supply for Core Circuits: +1.8V
VDD_PLL
39
M10
Power Supply for Analog PLL: +1.8V
VSS (GND)
9, 10, 21, 22,
35, 38, 40,
47, 50, 68,
70, 88, 89,
100, 110, 111,
122, 123,
133, 136,
154, 155,
174, 175,
190, 200,
201, 212,
213, 225,
226, 245, 246
F7, F8, F9,
F10, G6, G7,
G8, G9, G10,
G11, H6, H7,
H8, H9, H10,
H11, J6, J7,
J8, J9, J10,
J11, K6, K7,
K8, K9, K10,
K11, L8, L9
Ground.
Pin Description (continued)
Pin Name
ZL50064
Package
Coordinates
(256-pin
LQFP)
ZL50062
Package
Coordinates
(256-ball
PBGA)
Description


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