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ZL50062 Datasheet(PDF) 22 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 22 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
22
Zarlink Semiconductor Inc.
2.3
Input Frame Pulse and Generated Frame Pulse Alignment
The ZL50062 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. The ZL50064 only generates one frame pulse output, FP8o. There is a constant
throughput delay for data being switched from the input to the output of the device such that data which is input
during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 16, Frame
Boundary Conditions, ST-BUS Operation, and Figure 17, Frame Boundary Conditions, GCI-Bus Operation.
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates
The tFBOS is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to
the “AC Electrical Characteristics,” on page 52. Note that although the figure above shows the traditional setups of
the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to
accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the
opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register).
See the timing diagrams in “AC Electrical Characteristics,” on page 52 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50062/64, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8kHz). When bits
FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability.
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
CH3
CH7
CH0
CH1
CH2
BSTi/LSTi0-31
(16Mbps)
C8o
FP8o
BSTo/LSTo0-31
(2Mbps)
BSTo/LSTo0-31
(4Mbps)
BSTo/LSTo0-31
(8Mbps)
BSTo/LSTo0-31
(16Mbps)
CH2
CH1
CH0
CH6
CH5
CH4
CH3
CH2
CH0
CH4
CH5
CH10
CH9
CH8
CH11
CH
15
CH
14
CH
13
CH
12
CH
11
CH
10
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH
1
CH
0
CH
19
CH
18
CH
17
CH
16
CH
23
CH
22
CH
21
CH
20
CH1
CH
3
CH
2
CH
1
CH
0
CH
7
CH
6
CH
5
CH
4
CH
11
CH
10
CH
9
CH
8
CH
15
CH
14
CH
CH
12
13
CH
17
CH
16
CH
21
CH
20
CH
CH
18
19
CH
23
CH
22
FP8i
C8i
CH3
CH7
CH0
CH1
CH2
(2Mbps)
BSTi/LSTi0-31
(4Mbps)
BSTi/LSTi0-31
CH2
CH1
CH0
CH6
CH5
CH4
CH3
CH2
CH0
CH4
CH5
CH10
CH9
CH8
CH11
CH1
BSTi/LSTi0-31
(8Mbps)
tFBOS


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