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ZL50062 Datasheet(PDF) 25 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 25 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
25
Zarlink Semiconductor Inc.
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
Data Rate of 8Mbps
3.2
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072MHz). The advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which
converts to approximately 0ns, -15ns, -31ns or -46ns as shown in Figure 11.
C8i
7
2
3
4
5
6
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
Ch0
1
0
Ch127
sample at 3/4 point
FP8i
7
2
3
4
5
6
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
Ch0
1
0
Bit delay = 0 bit (Default)
Ch127
sample at 3/4 point
SMPL_MODE = LOW
C8i
7
2
3
4
5
6
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
Ch0
1
0
Ch127
sample at 2/4 point
FP8i
7
2
3
4
5
6
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
Ch0
1
0
3/4 sampling (Default)
Ch127
sample at 3/4 point
SMPL_MODE = HIGH
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Bit Delay = 3/4 bit
2/4 sampling


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