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ZL50062 Datasheet(PDF) 26 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 26 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
26
Zarlink Semiconductor Inc.
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps
4.0
Port high impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-31) and Backplane (BSTo0-31) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-31/BSTo0-31, to transmit bi-state
channel data.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-31/BSTo0-31, of the device to
invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-31. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See “Local Connection
Memory Bit Definition,” on page 34 and “Backplane Connection Memory Bit Definition,” on page 35 for
programming details.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-31/
BSTo0-31
0X
X
X
0
HIGH
0X
X
X
1
HI-Z
10
X
X
0
HIGH
10
X
X
1
HI-Z
110
X
0
HIGH
Table 1 - Local and Backplane Output Enable Control Priority
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
FP8o
System Clock
BSTo/LSTo0-31
Bit Advancement = 0
BSTo/LSTo0-31
Bit Advancement = -2
(Default)
Bit Advancement = -6
BSTo/LSTo0-31
Bit Advancement = -4
BSTo/LSTo0-31
131.072 MHz
Ch255
Ch255
Ch255
Ch255
Ch0
Ch0
Ch0
Ch0
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 4
Bit Advancement, 0


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