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ZL50062 Datasheet(PDF) 27 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 27 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
27
Zarlink Semiconductor Inc.
5.0
Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. Channels written
to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit
advancement have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), and output channel number (n). Table 2 describes the variable range for input streams and
Table 3 describes the variable range for output streams. The data throughput delay under various input channel
and output channel conditions can be summarized as:
T = 2 frames + (n - m)
110
X
1
HI-Z
111
00
HIGH
111
01
HI-Z
111
1
X
ACTIVE
(HIGH or LOW)
Input Stream
Data Rate
Input Channel
Number (m)
2Mbps
0 to 31
4Mbps
0 to 63
8Mbps
0 to 127
16Mbps
0 to 255
Table 2 - Variable Range for Input Streams
Output Stream
Data Rate
Output Channel
Number (n)
2Mbps
0 to 31
4Mbps
0 to 63
8Mbps
0 to 127
16Mbps
0 to 255
Table 3 - Variable Range for Output Streams
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-31/
BSTo0-31
Table 1 - Local and Backplane Output Enable Control Priority (continued)


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