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ZL50062 Datasheet(PDF) 29 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 29 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
29
Zarlink Semiconductor Inc.
6.0
Microprocessor Port
The 16K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 7, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.
7.0
Device Power-up, Initialization and Reset
7.1
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8V). The VDD_PLL and VDD_CORE supplies may be
powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3V.
All supplies may be powered-down simultaneously.
7.2
Initialization
Upon power up, the device should be initialized by applying the following sequence:
7.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-31 and BSTo0-31 are set to HIGH or high impedance, and all internal registers
and counters are reset to the default state.
The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250
µs must also be waited before the first microprocessor access is performed following
the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format.
1
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2Set ODE pin to LOW. This sets the LSTo0-31 outputs to HIGH or high impedance, dependent on the
LORS input value, and sets the BSTo0-31 outputs to HIGH or high impedance, dependent on BORS
input value. Refer to Pin Description for details of the LORS and BORS pins.
3
Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250
µs must also be applied before the first microprocessor access is
performed following the de-assertion of the RESET pin; this delay is required for determination of the
input frame pulse format.
4
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 8.3, Connection Memory Block Programming.
5Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.


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