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ZL50062 Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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ZL50062 Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
3 / 68 page ZL50062/4 Data Sheet 3 Zarlink Semiconductor Inc. Device Overview The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. All 64 input and 64 output streams must operate at the same data rate. The ZL50062/4 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: • Input-to-Output Unidirectional, supporting 16K x 16K switching • Backplane-to-Local Bi-directional, supporting 8K x 8K data switching, • Local-to-Backplane Bi-directional, supporting 8K x 8K data switching, • Backplane-to-Backplane Bi-directional, supporting 8K x 8K data switching. • Local-to-Local Bi-directional, supporting 8K x 8K data switching. The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI- Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period, the input frame pulse format is determined before switching begins. The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of the Backplane and Local ports. A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control signals. The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The ZL50062 and ZL50064 are each available in one package: • ZL50062: a 17mm x 17mm body, 1mm ball-pitch, 256-PBGA. • ZL50064: a 28mm x 28mm body, 0.40mm pin-pitch, 256-LQFP. |
Número de pieza similar - ZL50062 |
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Descripción similar - ZL50062 |
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