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ZL50062 Datasheet(PDF) 31 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 31 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
31
Zarlink Semiconductor Inc.
8.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the Control
Register and Block Programming Register values, respectively.
8.3.1
Memory Block Programming Procedure:
Set the MBP bit in the Control Register from LOW to HIGH.
•Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
Table 5 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 6.
Table 6 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125
µs, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
Source Stream Bit Rate
Source Stream No.
Source Channel No.
2Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:31
4Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:63
8Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:127
16Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:255
Table 4 - Local and Backplane Connection Memory Configuration
15
14
13
12
11
10
98
7654321
0
LBPD2
LBPD1
LBPD0
00000
0000000
0
15
14
13
12
11
10
9
876
543
210
BBPD2
BBPD1
BBPD0
0
000
000
000
000


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