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ZL50062 Datasheet(PDF) 33 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 33 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
33
Zarlink Semiconductor Inc.
10.2.2
Test Data Registers
10.2.2.1
The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50062/64 core logic.
10.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
10.2.2.3
The Device Identification Register
The JTAG device ID for the ZL50062/64 is 0C38E14B
H.
Version, Bits <31:28>:0000
Part No., Bits <27:12>:1100 0011 1000 1110
Manufacturer ID, Bits <11:1>:0001 0100 101
Header, Bit <0> (LSB):1
10.3
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
11.0
Memory Address Mappings
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
Address Bit
Description
A14
Selects memory or register access (0 = register, 1 = memory).
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
A13-A9
Stream address (0 - 31)
Streams 0 to 31 are used
A8-A0
Channel address (0 - 511)
Channels 0 to 31 are used when serial stream is at 2.048Mbps
Channels 0 to 63 are used when serial stream is at 4.096Mbps
Channels 0 to 127 are used when serial stream is at 8.192Mbps
Channels 0 to 255 are used when serial stream is at 16.384Mbps


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