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MC68HC908GR16A Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc

No. de Pieza. MC68HC908GR16A
Descripción  M68HC08 Microcontrollers
Descarga  270 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC68HC908GR16A Datasheet(HTML) 40 Page - Freescale Semiconductor, Inc

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MC68HC908GR16A Data Sheet, Rev. 1.0
40
Freescale Semiconductor
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from FLASH memory. While these operations must be
performed in the order shown, other unrelated operations may occur
between the steps.
2.6.5 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0.
During the programming cycle, make sure that all addresses being written to fit within one of the ranges
specified above. Attempts to program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH memory (Figure 2-4 is a flowchart
representation).
NOTE
Only bytes which are currently $FF may be programmed.
1.
Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2.
Read the FLASH block protect register.
3.
Write any data to any FLASH address within the row address range desired.
4.
Wait for a time, tNVS (minimum 10 µs).
5.
Set the HVEN bit.
6.
Wait for a time, tPGS (minimum 5 µs).
7.
Write data to the FLASH address to be programmed.
8.
Wait for a time, tPROG (minimum 30 µs).
9.
Repeat step 7 and 8 until all the bytes within the row are programmed.
10.
Clear the PGM bit.(1)
11.
Wait for a time, tNVH (minimum 5 µs).
12.
Clear the HVEN bit.
13.
After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
within the FLASH array memory space such as the COP control register
(COPCTL) at $FFFF.
NOTE
It is highly recommended that interrupts be disabled during program/ erase
operations.


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