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MC68HC908GR16A Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc

No. de Pieza. MC68HC908GR16A
Descripción  M68HC08 Microcontrollers
Descarga  270 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC68HC908GR16A Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc

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I/O Registers
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
53
3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from
left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit
result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion
completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will
be lost until the ADRH and ADRL reads are completed.
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the 10-bit result. All other bits read as 0.
The ADRL register holds the eight LSBs of the 10-bit result. ADRH and ADRL are updated each time an
ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address:
$003D
ADRH
Bit 7
654321
Bit 0
Read:
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
Address:
$003E
ADRL
Read:
AD1
AD0
000000
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
Address:
$003D
ADRH
Bit 7
654321
Bit 0
Read:
000000
AD9
AD8
Write:
Reset:
Unaffected by reset
Address:
$003E
ADRL
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)


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