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MC68HC908GR16A Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc

No. de Pieza. MC68HC908GR16A
Descripción  M68HC08 Microcontrollers
Descarga  270 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC68HC908GR16A Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc

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Functional Description
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
63
Table 4-3 provides numeric examples (register values are in hexadecimal notation):
4.3.7 Special Programming Exceptions
The programming method described in 4.3.6 Programming the PLL does not account for two possible
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
A 0 value for N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
See 4.3.8 Base Clock Selector Circuit.
4.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
Table 4-3. Numeric Example
fBUS (MHz)
fRCLK (MHz)
PCTL
E
PMSH,L
N
PMRS
L
1.0
2.0
0
002
38
2.0
2.0
0
004
70
4.0
2.0
1
008
70
8.0
2.0
2
010
70
2.0
4.0
0
002
70
4.0
4.0
1
004
70
5.0
4.0
2
005
46
8.0
4.0
2
008
70
2.4576
4.9152
1
002
45
4.9152
4.9152
2
004
45
7.3728
4.9152
2
006
67
2.0
8.0
0
001
70
4.0
8.0
1
002
70
6.0
8.0
2
003
54
8.0
8.0
2
004
70


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