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MC68HC908GR16A Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc
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FREESCALE [Freescale Semiconductor, Inc]
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MC68HC908GR16A Datasheet(HTML) 72 Page - Freescale Semiconductor, Inc
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Clock Generator Module (CGM)
MC68HC908GR16A Data Sheet, Rev. 1.0
4.7.2 Stop Mode
If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
4.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 188.8.131.52 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write the PLL control register during the break state without affecting the PLLF bit.
4.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
4.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz
Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz
±5 kHz. Five kHz = 5% of the
100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
4.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
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