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MC68HC908GR16A Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

No. de Pieza. MC68HC908GR16A
Descripción  M68HC08 Microcontrollers
Descarga  270 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC68HC908GR16A Datasheet(HTML) 76 Page - Freescale Semiconductor, Inc

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Configuration Register (CONFIG)
MC68HC908GR16A Data Sheet, Rev. 1.0
76
Freescale Semiconductor
TBMCLKSEL— Timebase Clock Select Bit
TBMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See Chapter 4 Clock Generator Module (CGM) for
a more detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module (CGM). This function is used to keep the timebase running while
the reset of the MCU stops. See Chapter 17 Timebase Module (TBM). When clear, oscillator will cease
to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator
in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
ESCIBDSRC — SCI Baud Rate Clock Source Bit
ESCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See Chapter 14 Enhanced Serial
Communications Interface (ESCI) Module.
1 = Internal bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 6 Computer Operating
Properly (COP) Module
1 = COP timeout period = 8176 COPCLK cycles
0 = COP timeout period = 262,128 COPCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
Address:
$001F
Bit 7
654321
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3
SSREC
STOP
COPD
Write:
Reset:
0000
See note
000
Note: LVI5OR3 bit is only reset via POR (power-on reset).
Figure 5-2. Configuration Register 1 (CONFIG1)


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