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MC68HC908GR16A Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc

No. de Pieza. MC68HC908GR16A
Descripción  M68HC08 Microcontrollers
Descarga  270 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC68HC908GR16A Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc

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Functional Description
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor
77
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit
(LVI)). The voltage mode selected for the LVI should match the operating VDD (see Chapter 20
Electrical Specifications) for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
If the system clock source selected is the internal oscillator or the external crystal and the
OSCENINSTOP configuration bit is not set, the oscillator will be disabled during stop mode. The short
stop recovery does not provide enough time for oscillator stabilization and for this reason the SSREC
bit should not be set.
The system stabilization time for power-on reset and long stop recovery (both 4096 CGMXCLK cycles)
gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the
MCU is not protected from a low-power condition. However, when using the short stop recovery
configuration option, the 32-CGMXCLK delay must be greater than the LVI’s turn on time to avoid a
period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP) Module.
1 = COP module disabled
0 = COP module enabled


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