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ADAU1328 Datasheet(PDF) 6 Page - Analog Devices

No. de Pieza. ADAU1328
Descripción  2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
Descarga  32 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADAU1328 Datasheet(HTML) 6 Page - Analog Devices

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ADAU1328
Rev. 0 | Page 6 of 32
DIGITAL FILTERS
Table 5.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
All modes, typ @ 48 kHz
Pass Band
0.4375 fS
21
kHz
Pass-Band Ripple
±0.015
dB
Transition Band
0.5 fS
24
kHz
Stop Band
0.5625 fS
27
kHz
Stop-Band Attenuation
79
dB
Group Delay
22.9844/fS
479
μs
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typ @ 48 kHz
0.4535 fS
22
kHz
96 kHz mode, typ @ 96 kHz
0.3646 fS
35
kHz
192 kHz mode, typ @ 192 kHz
0.3646 fS
70
kHz
Pass-Band Ripple
48 kHz mode, typ @ 48 kHz
±0.01
dB
96 kHz mode, typ @ 96 kHz
±0.05
dB
192 kHz mode, typ @ 192 kHz
±0.1
dB
Transition Band
48 kHz mode, typ @ 48 kHz
0.5 fS
24
kHz
96 kHz mode, typ @ 96 kHz
0.5 fS
48
kHz
192 kHz mode, typ @ 192 kHz
0.5 fS
96
kHz
Stop Band
48 kHz mode, typ @ 48 kHz
0.5465 fS
26
kHz
96 kHz mode, typ @ 96 kHz
0.6354 fS
61
kHz
192 kHz mode, typ @ 192 kHz
0.6354 fS
122
kHz
Stop-Band Attenuation
48 kHz mode, typ @ 48 kHz
70
dB
96 kHz mode, typ @ 96 kHz
70
dB
192 kHz mode, typ @ 192 kHz
70
dB
Group Delay
48 kHz mode, typ @ 48 kHz
25/fS
521
μs
96 kHz mode, typ @ 96 kHz
11/fS
115
μs
192 kHz mode, typ @ 192 kHz
8/fS
42
μs
TIMING SPECIFICATIONS
−40°C < TA < +85°C, DVDD = 3.3 V ± 10%.
Table 6.
Parameter
Condition
Comments
Min
Max
Unit
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
MCLK duty cycle
DAC/ADC clock source = PLL clock @
256 fS, 384 fS, 512 fS, 768 fS
40
60
%
tMH
DAC/ADC clock source = direct MCLK @
512 fS (bypass on-chip PLL)
40
60
%
fMCLK
MCLK frequency
PLL mode, 256 fS reference
6.9
13.8
MHz
fMCLK
Direct 512 fS mode
27.6
MHz
tPDR
RST low
15
ns
tPDRR
RST recovery
Reset to active output
4096
tMCLK
PLL
Lock Time
MCLK and LRCLK input
10
ms
256 fS VCO Clock, Output Duty Cycle MCLKO pin
40
60
%


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