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CS5302 Datasheet(PDF) 5 Page - ON Semiconductor

No. de Pieza. CS5302
Descripción  Two−Phase Buck Controller with Integrated Gate Drivers and 4−Bit DAC
Descarga  17 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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CS5302 Datasheet(HTML) 5 Page - ON Semiconductor

 
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ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 10 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 μF, CREF = 0.1 μF, DAC Code 1001, CVCC = 1.0 μF,
ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATE(H)
V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V
60 mV step applied between VCSX and VCREF
350
515
ns
Channel Start Up Offset
V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V;
Measure V(COMP) when GATE(H)1, (H)2,
switch high
0.3
0.4
0.5
V
Gate(H) and Gate(L)
High Voltage (AC)
Note 4 Measure VCCLX − Gate(L)X or
VCCHX − Gate(H)X
0
1.0
V
Low Voltage (AC)
Note 4 Measure Gate(L)X or Gate(H)X
0
0.5
V
Rise Time Gate(H)X
1.0 V < GATE < 8.0 V; VCCHX = 10 V
35
80
ns
Rise Time Gate(L)X
1.0 V < GATE < 8.0 V; VCCLX = 10 V
35
80
ns
Fall Time Gate(H)X
8.0 V > GATE > 1.0 V; VCCHX = 10 V
35
80
ns
Fall Time Gate(L)X
8.0 V > GATE > 1.0 V; VCCLX = 10 V
35
80
ns
Gate(H) to Gate(L) Delay
Gate(H)X < 2.0 V, Gate(L)X > 2.0 V
30
65
110
ns
Gate(L) to Gate(H) Delay
Gate(L)X < 2.0 V, Gate(H)X > 2.0 V
30
65
110
ns
GATE Pull−down
Force 100 μA into Gate Driver with no power
applied to VCCHX and VCCLX = 2 V.
1.2
1.6
V
Oscillator
Switching Frequency
Measure any phase (ROSC = 32.4 k)
300
400
500
kHz
Switching Frequency
Note 4 Measure any phase (ROSC = 63.4 k)
150
200
250
kHz
Switching Frequency
Note 4 Measure any phase (ROSC = 16.2 k)
600
800
1000
kHz
ROSC Voltage
1.0
V
Phase Delay
165
180
195
deg
Adaptive Voltage Positioning
VDRP Output Voltage to DACOUT
Offset
CS1 = CS2 = CSREF, VFB = COMP
Measure VDRP − COMP
−15
15
mV
Maximum VDRP Voltage
(CS1 = CS2) − CREF = 50 mV,
VFB = COMP, Measure VDRP − COMP
240
310
380
mV
Current Sense Amp to VDRP Gain
2.4
3.0
3.8
V/V
Current Sensing and Sharing
CSREF Input Bias Current
V(CSx) = V(CSREF) = 0 V
0.5
4.0
μA
CS1−CS2 Input Bias Current
V(CSx) = V(CSREF) = 0 V
0.2
2.0
μA
Current Sense Amplifiers Gain
2.8
3.15
3.53
V/V
Current Sense Amp Mismatch
Note 4 0 ≤ (CSx − CSREF) ≤ 50 mV
−5.0
5.0
mV
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4
0
VCCL − 2
V
Current Sense Input to ILIM Gain
0.25 V < ILIM < 1.20 V
5.0
6.25
8.0
V/V
Current Limit Filter Slew Rate
Note 4
4.0
10
26
mV/μs
4. Guaranteed by design. Not tested in production.


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