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CS5302 Datasheet(PDF) 13 Page - ON Semiconductor |
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CS5302 Datasheet(HTML) 13 Page - ON Semiconductor |
13 / 17 page CS5302 http://onsemi.com 13 order to reduce voltage excursions during transients. Adaptive voltage positioning can reduce peak−peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is stepped up and set lower than nominal during heavy loads to reduce overshoot when the load current is stepped up. For low current applications a droop resistor can provide fast accurate adaptive positioning. However, at high currents the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1.0 mΩ resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond quickly to changes in load current. Figure 14 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. Adaptive Positioning Adaptive Positioning Normal Fast Slow Limits Figure 14. Adaptive Positioning The CS5302 can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram on page 2.) To set the no−load positioning, a resistor is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to increase the output voltage. The VFB bias current is dependent on the value of ROSC. See Figure 4. During no load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor. When output current increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to decrease. The VFB and VDRP pins take care of the slower and DC voltage positioning. The first few μs are controlled primarily by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Note: Large levels of adaptive positioning can cause pulse width jitter. Error Amp Compensation The transconductance error amplifier requires a capacitor between the COMP pin and GND. Use of values less than 1nF may result in error amp oscillation of several MHz. The capacitor between the COMP pin and the inverting error amplifier input and the parallel resistance of the VFB resistor and the VDRP resistor are used to roll off the error amp gain. The gain is rolled off at a high enough frequency to give a quick transient response, but low enough to cross zero dB well below the switching frequency to minimize ripple and noise on the COMP pin. UVLO The CS5302 has undervoltage lockout functions connected to two pins. One, intended for the logic and low−side drivers, with a 4.4 V turn−on threshold is connected to the VCCL pin. A second, intended for the high side drivers, powered from 12 V has a 9.0 V threshold is connected to the VCCH1 pin. Both thresholds must be exceeded for the converter to start. Soft Start and Hiccup Mode A capacitor between the Soft Start pin and GND controls Soft Start and hiccup mode slopes. A 0.1 μF capacitor with the 30 μA charge current will allow the output to ramp up at 0.3 V/ms or 1.5 V in 5.0 ms at start−up. When a fault is detected due to overcurrent or UVLO the converter will enter a low duty cycle hiccup mode. During hiccup mode the converter will not switch from the time a fault is detected until the Soft Start capacitor has discharged below the Soft Start Discharge Threshold and then charged back up above the Channel Start Up Offset. The Soft Start pin will disable the converter when pulled below 0.3 V. Layout Guidelines With the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically, a multi−layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to reroute the currents away from the controller. The slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate |
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