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ADN2806ACPZ Datasheet(PDF) 7 Page - Analog Devices |
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ADN2806ACPZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 20 page ADN2806 Rev. 0 | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TEST1 1 VCC 2 VREF 3 TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE NIN 4 PIN 5 NC 6 NC 7 VEE 8 ADN2806* * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. NC=NO CONNECT PIN 1 INDICATOR Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 TEST1 Connect to VCC. 2 VCC P Power for Limiting Amplifier, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 NC No Connect 7 NC No Connect 8 VEE P GND for Limiting Amplifier, LOS. 9 NC No Connect 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss-of-Lock Indicator. LVTTL active high. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 22 NC No Connect 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 TEST2 Connect to VCC. Exposed Pad Pad P Connect to GND. 1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. |
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