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NB3N551 Datasheet(PDF) 2 Page - ON Semiconductor

No. de Pieza. NB3N551
Descripción  3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
Descarga  5 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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NB3N551 Datasheet(HTML) 2 Page - ON Semiconductor

   
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NB3N551
http://onsemi.com
2
OE
1
0
Function
Enable
Disable
Table 1. OE, Output Enable Function
PIN DESCRIPTION
Pin #
Name
Type
Description
1
ICLK
(LV)CMOS/(LV)TTL Input
Clock Input. Internal pull−up resistor.
2
Q1
(LV)CMOS/(LV)TTL Output
Clock Output 1
3
Q2
(LV)CMOS/(LV)TTL Output
Clock Output 2
4
Q3
(LV)CMOS/(LV)TTL Output
Clock Output 3
5
Q4
(LV)CMOS/(LV)TTL Output
Clock Output 4
6
GND
Power
Negative supply voltage; Connect to ground, 0 V
7
VDD
Power
Positive supply voltage (3.0 V to 5.5 V)
8
OE
(LV)CMOS/(LV)TTL Input
Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pull−up resistor. Three−states outputs when LOW.
MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD
Positive Power Supply
GND = 0 V
7.0
V
VI/VO
Input/Output Voltage
t ≤ 1.5 ns
GND–1.5 ≤ VI/VO ≤ VDD+1.5
V
TA
Operating Temperature Range, Industrial
≥ −40 to ≤ +85
_C
Tstg
Storage Temperature Range
−65 to +150
_C
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
SOIC−8
190
130
_C/W
_C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
SOIC−8
41 to 44
_C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
DFN−8
DFN−8
129
84
_C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
ATTRIBUTES
Characteristic
Value
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL−94 code V−0 @ 0.125 in
Transistor Count
531 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.


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