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NB3N551 Datasheet(PDF) 3 Page - ON Semiconductor

No. de Pieza. NB3N551
Descripción  3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
Descarga  5 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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NB3N551 Datasheet(HTML) 3 Page - ON Semiconductor

   
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NB3N551
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3
DC CHARACTERISTICS (VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Min
Typ
Max
Unit
IDD
Power Supply Current @ 135 MHz, No Load, VDD = 3.3 V
20
40
mA
VOH
Output HIGH Voltage – IOH = −25 mA, VDD = 3.3 V
2.4
V
VOL
Output LOW Voltage – IOL = 25 mA
0.4
V
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
VDD − 0.4
V
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD/2)+0.7
3.8
V
VIL, ICLK
Input LOW Voltage, ICLK
(VDD/2)−0.7
V
VIH, OE
Input HIGH Voltage, OE
2.0
VDD
V
VIL, OE
Input LOW Voltage, OE
0
0.8
V
ZO
Nominal Output Impedance
20
W
RPU
Input Pull−up Resistor, OE
220
kW
CIN
Input Capacitance, OE
5.0
pF
IOS
Short Circuit Current
± 50
mA
DC CHARACTERISTICS (VDD = 4.5 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Min
Typ
Max
Unit
IDD
Power Supply Current @ 135 MHz, No Load, VDD = 5.0 V
50
95
mA
VOH
Output HIGH Voltage – IOH = −35 mA
2.4
V
VOL
Output LOW Voltage – IOL = 35 mA
0.4
V
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
VDD – 0.4
V
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD/2) + 1
5.5
V
VIL, ICLK
Input LOW Voltage, ICLK
(VDD/2) − 1
V
VIH, OE
Input HIGH Voltage, OE
2.0
VDD
V
VIL, OE
Input LOW Voltage, OE
0
0.8
V
ZO
Nominal Output Impedance
20
W
RPU
Input Pull−up Resistor, OE
220
kW
CIN
Input Capacitance, OE
5.0
pF
IOS
Short Circuit Current
±80
mA
AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Min
Typ
Max
Unit
fin
Input Frequency
180
MHz
tjitter (pd)
Period Jitter (RMS, 1σ)
2.0
ps
tr/tf
Output rise and fall times; 0.8 V to 2.0 V
0.5
1.0
ns
tpd
Propagation Delay, CLK to Qn, 0 − 180 MHz, (Note 4)
1.5
3.0
6.0
ns
tskew
Output−to−output skew; (Note 5)
50
160
ps
3. Outputs loaded with external RL = 33−W series resistor and CL = 15 pF to GND for proper operation. Duty cycle out = duty in. A 0.01 mF
decoupling capacitor should be connected between VDD and GND. A 33 W series terminating resistor may be used on each clock output
if the trace is longer than 1 inch.
4. Measured with rail−to−rail input clock.
5. Measured on rising edges at VDD ÷ 2.


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