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NB3N3001 Datasheet(PDF) 7 Page - ON Semiconductor |
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NB3N3001 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 8 page NB3N3001 http://onsemi.com 7 PC Board Layout Example Figure 11 shows a representative board layout for the NB3N3001. There exists many different potential board layouts and the one pictured is but one. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through−hole HC49 package. The footprints of other components in this example are listed in Table 11. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. The important aspect of the layout in Figure 11 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NB3N3001 outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. The voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Table 11. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 Figure 11. PC Board Layout C2 C1 Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Driver Device Receiver Device QD Q D Zo = 50 W Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V ORDERING INFORMATION Device Package Shipping† NB3N3001DTG TSSOP8 4.4 mm (Pb−Free) 100 Units / Rail NB3N3001DTR2G TSSOP8 4.4 mm (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. |
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