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ADN2813 Datasheet(PDF) 11 Page - Analog Devices

No. de Pieza. ADN2813
Descripción  Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
Descarga  28 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2813 Datasheet(HTML) 11 Page - Analog Devices

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ADN2813
Rev. 0 | Page 11 of 28
Table 6. Internal Register Map1
Reg.
Name
R/W
Address
D7
D6
D5
D4
D3
D2
D1
D0
FREQ0
R
0x0
MSB
LSB
FREQ1
R
0x1
MSB
LSB
FREQ2
R
0x2
0
MSB
LSB
RATE
R
0x3
COARSE_RD[8] MSB
Coarse Data Rate Readback
COARSE_RD[1]
MISC
R
0x4
x
x
LOS
Status
Static
LOL
LOL
Status
Data Rate
Measure
Complete
x
COARSE_RD[0] LSB
CTRLA
W
0x8
FREF Range
Data Rate/DIV_FREF Ratio
Measure
Data Rate
Lock to
Reference
CTRLB
W
0x9
Config.
LOL
Reset
MISC[4]
System
Reset
0
Reset
MISC[2]
0
0
0
CTRLC
W
0x11
0
0
0
0
0
Config. LOS
SQUELCH
Mode
Output Boost
1 All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
LOS Status
Static LOL
LOL Status
Data Rate Measurement
Complete
Coarse Rate
Readback LSB
D7
D6
D5
D4
D3
D2
D1
D0
x
x
0 = No loss of signal
0 = Waiting for next LOL
0 = Locked
0 = Measuring data rate
x
COARSE_RD[0]
1 = Loss of signal
1 = Static LOL until reset
1 = Acquiring
1 = Measurement complete
Table 8. Control Register, CTRLA1
FREF Range
Data Rate/Div_FREF Ratio
Measure Data Rate
Lock to Reference
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10 MHz to 20 MHz
0
0
0
0
1
Set to 1 to measure data rate
0 = Lock to input data
0
1
20 MHz to 40 MHz
0
0
0
1
2
1 = Lock to reference clock
1
0
40 MHz to 80 MHz
0
0
1
0
4
1
1
80 MHz to 160 MHz
n
2n
1
0
0
0
256
1 Where DIV_F
REF
is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
Reset MISC[2]
D7
D6
D5
D4
D3
D2
D1
D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by 0
to reset ADN2813
Set
to 0
Write a 1 followed by 0
to reset MISC[2]
Set
to 0
Set
to 0
Set
to 0
Table 10. Control Register, CTRLC
Config. LOS
SQUELCH Mode
Output Boost
D7
D6
D5
D4
D3
D2
D1
D0
0 = Active high LOS
0 = SQUELCH CLK and DATA
0 = Default output swing
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
1 = Active low LOS
1 = SQUELCH CLK or DATA
1 = Boost output swing


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