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ADN2815 Datasheet(PDF) 1 Page - Analog Devices

No. de Pieza. ADN2815
Descripción  Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC
Descarga  24 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2815 Datasheet(HTML) 1 Page - Analog Devices

 
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Continuous Rate 10 Mb/s to 1.25 Gb/s
Clock and Data Recovery IC
ADN2815
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband crossconnects and routers
GENERAL DESCRIPTION
The ADN2815 provides the receiver functions of quantization
and clock and data recovery for continuous data rates from
10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all
data rates without the need for an external reference clock or
programming. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The ADN2815 is available in a compact 5 mm × 5 mm 32-lead
LFCSP.
FUNCTIONAL BLOCK DIAGRAM
2
LOL
DATAOUTP/
DATAOUTN
DRVEE DVCC
DRVCC
DVEE
ADN2815
CLKOUTP/
CLKOUTN
2
VCC
VEE
CF1
CF2
PIN
NIN
VREF
BUFFER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY
DETECT
DATA
RE-TIMING
LOOP
FILTER
LOOP
FILTER
REFCLKP/REFCLKN
(OPTIONAL)
Figure 1.


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