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ADN2817 Datasheet(PDF) 19 Page - Analog Devices

No. de Pieza. ADN2817
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Descarga  35 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2817 Datasheet(HTML) 19 Page - Analog Devices

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Preliminary Technical Data
ADN2817/ADN2818
Rev.Pr A | Page 19 of 35
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2817/ADN2818 acquires frequency from the data
over a range of data frequencies from 12.3 Mb/s to 2.7 Gb/s.
The lock detector circuit compares the frequency of the VCO
and the frequency of the incoming data. When these
frequencies differ by more than 1000 ppm, LOL is asserted. This
initiates a frequency acquisition cycle. The VCO frequency is
reset to the bottom of its range, which is 12.3 MHz. The
frequency detector then compares this VCO frequency and the
incoming data frequency and increments the VCO frequency, if
necessary. Initially, the VCO frequency is incremented in large
steps to aid fast acquisition. As the VCO frequency approaches
the data frequency, the step size is reduced until the VCO
frequency is within 250 ppm of the data frequency, at which
point LOL is de-asserted.
Once LOL is de-asserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pins 14 and 15. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 uF capacitor should be greater than 300 MΩ.
LOCK DETECTOR OPERATION
The lock detector on the ADN2817/ADN2818 has three modes
of operation: normal mode, REFCLK mode, and static LOL
mode.
Normal Mode
In normal mode, the ADN2817/ADN2818 is a continuous rate
CDR that locks onto any data rate from 12.3 Mb/s to 2.7 Gb/s
without the use of a reference clock as an acquisition aid. In this
mode, the lock detector monitors the frequency difference
between the VCO and the input data frequency, and de-asserts
the loss of lock signal, which appears on LOL Pin 16, when the
VCO is within 250 ppm of the data frequency. This enables the
D/PLL, which pulls the VCO frequency in the remaining
amount and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
begins a new frequency acquisition starting at the lowest point
in the VCO operating range, 12.3 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
within 250 ppm frequency error. This hysteresis is shown in
Figure 19.
LOL
0
–250
250
1000
fVCO ERROR
(ppm)
–1000
1
Figure 19. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2817/ADN2818 VCO. Lock to reference mode is
enabled by setting CTRLA[0] to 1. The user also needs to write
to the CTRLA[7:6] and CTRLA[5:2] bits in order to set the
reference frequency range and the divide ratio of the data rate
with respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss of lock signal, which appears on the LOL Pin 16, is de-
asserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
re-acquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 19.
Static LOL Mode
The ADN2817/ADN2818 implements a static LOL feature,
which indicates if a loss of lock condition has ever occurred and
remains asserted, even if the ADN2817/ADN2818 regains lock,
until the static LOL bit is manually reset. The I2C register bit,
MISC[4], is the static LOL bit. If there is ever an occurrence of a
loss of lock condition, this bit is internally asserted to logic
high. The MISC[4] bit remains high even after the
ADN2817/ADN2818 has re-acquired lock to a new data rate.
This bit can be reset by writing a 1 followed by 0 to I2C Register
Bit CTRLB[6]. Once reset, the MISC[4] bit remains de-asserted
until another loss of lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2817/ADN2818 is in acquisition mode and de-asserts
when the ADN2817/ADN2818 has re-acquired lock.


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