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ADN2817 Datasheet(PDF) 20 Page - Analog Devices

No. de Pieza. ADN2817
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Descarga  35 Pages
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Fabricante  AD [Analog Devices]
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ADN2817 Datasheet(HTML) 20 Page - Analog Devices

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Preliminary Technical Data
Rev. PrA | Page 20 of 35
The ADN2817/ADN2818 provides a harmonic detector, which
detects whether or not the input data has changed to a lower
harmonic of the data rate that the VCO is currently locked onto.
For example, if the input data instantaneously changes from
OC-48, 2.488 Gb/s, to an OC-12, 622.080 Mb/s bit stream, this
could be perceived as a valid OC-48 bit stream, because the
OC-12 data pattern is exactly 4× slower than the OC-48
pattern. So, if the change in data rate is instantaneous, a 101
pattern at OC-12 would be perceived by the
ADN2817/ADN2818 as a 111100001111 pattern at OC-48. If
the change to a lower harmonic is instantaneous, a typical CDR
could remain locked at the higher data rate.
The ADN2817/ADN2818 implements a harmonic detector that
automatically identifies whether or not the input data has
switched to a lower harmonic of the data rate that the VCO is
currently locked onto. When a harmonic is identified, the LOL
pin is asserted and a new frequency acquisition is initiated. The
ADN2817/ADN2818 automatically locks onto the new data
rate, and the LOL pin is de-asserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate the VCO is currently locked
onto, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2817/ADN2818
automatically locks onto the new data rate.
The time to detect lock to harmonic is
16,384 × (Td/ρ)
1/Td is the new data rate. For example, if the data rate is
switched from OC-48 to OC-12, then Td = 1/622 MHz.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2817/ADN2818 is placed in lock to reference
mode, the harmonic detector is disabled.
The limiting amplifier on the ADN2817 has differential inputs
(PIN/NIN), which are internally terminated with 50 Ω to an
on-chip voltage reference (VREF = 2.5 V typically). The inputs
are typically ac-coupled externally, although dc coupling is
possible as long as the input common mode voltage remains
above 2.5 V (see Figure 28, Figure 29, and Figure 30 in the
Applications Information section). Input offset is factory
trimmed to achieve better than 6 mV typical sensitivity with
minimal drift. The limiting amplifier can be driven
differentially or single-ended.
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/N inputs. If no adjustment of the slice
level is needed, SLICEP/N should be tied to VEE. The gain of
the slice adjustment is ~0.1 V/V.
If the user is not using the BER monitoring function, sample
phase adjustment can be utilized to optimize the horizontal
sampling point of the incoming data eye. The ADN2817
automatically centers the sampling point to the best of its ability.
However, sample phase adjustment could be used to
compensate for any static phase offset of the CDR and duty
cycle distortion of the incoming eye. Sample phase adjustment
is applied to the incoming eye via the PHASE register. It is
important to note that sample phase adjustment can not be used
if the user is utilising the BER monitoring capability. This is
because the BER monitoring circuit requires control of the
sample phase adjustment circuitry. Also, using the sample phase
adjustment capability uses an additional 180mW of power.
The receiver front end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point-versus-
resistor value is illustrated in Figure 5. If the input level to the
ADN2817/ADN2818 drops below the programmed LOS
threshold, the output of the LOS detector, LOS Pin 22, is
asserted to a Logic 1. The LOS detector’s response time is ~500
ns by design, but is dominated by the RC time constant in ac-
coupled applications. The LOS pin defaults to active high.
However, by setting Bit CTRLC[2] to 1, the LOS pin is
configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means
that, if the input level drops below the programmed LOS
threshold causing the LOS pin to assert, the LOS pin is not de-
asserted until the input level has increased to 6 dB (2×) above
the LOS threshold (see Figure 20).

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