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ADN2817 Datasheet(PDF) 23 Page - Analog Devices

No. de Pieza. ADN2817
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Descarga  35 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2817 Datasheet(HTML) 23 Page - Analog Devices

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Preliminary Technical Data
ADN2817/ADN2818
Rev.Pr A | Page 23 of 35
and returns a ratio of the two frequencies to 0.01% (100 ppm).
The accuracy error of the reference clock is added to the
accuracy of the ADN2817/ADN2818 data rate measurement.
For example, if a 100-ppm accuracy reference clock is used, the
total accuracy of the measurement is within 200 ppm.
The reference clock can range from 12.3 MHz and 200 MHz.
The ADN2817/ADN2818 expects a reference clock between
12.3 MHz and 25 MHz by default. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
user needs to configure the ADN2817/ADN2818 to use the
correct reference frequency range by setting two bits of the
CTRLA register, CTRLA[7:6]. Using the reference clock to
determine the frequency of the incoming data does not affect
the manner in which the part locks onto data. In this mode, the
reference clock is used only to determine the frequency of the
data. For this reason, the user does not need to know the data
rate to use the reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2817/ADN2818. This bit is
level sensitive and does not need to be reset to perform
subsequent frequency measurements.
Step 2: Reset MISC[2] by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
Step 3: Read back MISC[2]. If it is 0, then the measurement is
not complete. If it is 1, then the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Step 4: Read back the data rate from registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
Use the following equation to determine the data rate:
[]
()
)
_
14
(
2
/
0
..
22
RATE
SEL
REFCLK
DATARATE
f
FREQ
f
+
×
=
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),
FREQ1[7:0], and FREQ0[7:0] (LSByte).
Table 13.
D22
D21...D17
D16
D15
D14...D9
D8
D7
D6...D1
D0
FREQ2[6:0]
FREQ1[7:0]
FREQ0[7:0]
fDATARATE is the data rate (Mb/s).
fREFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting would be [01],
because the reference frequency would fall into the 25 MHz to
50 MHz range. Assume for this example that the input data rate
is 2.488 Gb/s (OC-48). After following Steps 1 through 4, the
value that is read back on FREQ[22:0] = 0x26E010, which is
equal to 2.5477 × 106. Plugging this value into the equation
yields
(
)
(
)
Gb/s
488
.
2
2
/
6
e
32
6
e
5477
.
2
)
1
14
(
=
×
+
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Steps 2 through 4 to read back the new data rate.
Note: A data rate readback is valid only if LOL is low. If LOL is
high, the data rate readback is invalid.


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