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ADN2817 Datasheet(PDF) 24 Page - Analog Devices

No. de Pieza. ADN2817
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Descarga  35 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2817 Datasheet(HTML) 24 Page - Analog Devices

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ADN2817/ADN2818
Preliminary Technical Data
Rev. PrA | Page 24 of 35
Additional Features Available via the I2C Interface
Coarse Data Rate Readback
The data rate can be read back over the I2C interface to
approximately +10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is de-asserted. The 8 MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 14 provides coarse data rate readback to within ±10%.
Relative Bit Error Rate Monitor
The ADN2817 has a Bit Error Rate (BER) measurement feature
that provides for an estimation of the actual bit error rate of the
IC. The feature also allows data eye jitter profiling and Q-factor
estimation.
The implementation relies on the fact that by knowing the BER
at sampling phases offset from the ideal sampling phase, it is
possible to extrapolate to obtain an estimate of the BER at the
actual sampling instant. This extrapolation relies on the
assumption that the input jitter is composed of deterministic
and random (gaussian) components. The implementation
requires off-chip control and data processing to estimate the
actual BER.
Brief Overview of Modes of Operation
Two modes of operation are available for the BER feature. Only
one mode can be operational at a time. The primary mode is to
scan the input eye in the range of +/-0.5UI of the data centre,
and read the measured pseudo-BER over the I2C. The user will
then use the previously discussed algorithms to determine the
BER. Using the BER feature in this way provides for the greatest
accuracy in BER estimation as the magnitude of both Random
(Gaussian) Jitter and Deterministic Jitter can be estimated, and
used to predict the actual BER. In the secondary mode the part
autonomously samples the PBER at 0.1UI offset, decodes this
value to provide an estimate of the input BER. This estimate is
output vis a DAC as an analogue voltage output.
Primary Mode
Power Saving
There are three power modes in primary mode.
In "BER Off " mode all the BER circuitry will be powered down,
and operation of the DLL will be the same as the ADN2812.
In "BER On" mode all of the BER logic and all the clock phase
interpolators will be powered up. The user can perform a PBER
measurement through the I2C. The clock signal from the VCO
passes through the clock phase interpolator, to the NDC and
DDC.
In "BER Standby" mode the BER logic and the DDC clock phase
interpolators are powered down. The dummy clock phase
interpolator is powered up. The clock signal from the VCO
passes through the clock phase interpolator to the NDC only.
These modes are defined to allow optimal power saving
opportunities. It is not possible to switch between BER Off
mode and BER On mode without loosing lock. This is because
we must route the NDC clock signal through different circuitry
in going from one mode to the other. Switching between BER
Standby mode and BER On mode is achieved without
interrupting the data recovery. The incremental power between
BER Off and BER Standby mode is 88mW, and that between
BER Off and BER On modes is 177mW.
BER On Mode
The BER On mode of operation allows the user to scan the
incoming data eye in the time dimension and build up a profile
of the BER statistics.
User Protocol
User Powers Up BER Circuitry, through I2C.
User initiates BER measurement. Sample Phase Offset &
Number of data bits to be counted (Numbits - choice between
2^18, 2^21, 2^24, 2^27, 2^30, 2^33, 2^36 or 2^39) are supplied
by user, through I2C.
Apply Reset Pulse to BER through I2C.
BER Logic indicates End Of BER Measurement with EOBM
signal and updates the number of counted errors on
NumErrors<39:0>
User must poll the I2C to determine if EOBM has been
asserted.
User reads back NumErrors<39:0>, through the I2C. BER for
programmed sample phase is calculated as
Numerrors/Numbits.
User Powers Down BER, or requests another BER measurement
(step 2).
The user will sweep the phase over 0 to 1 UI, to get the BER
profile required.
Note: The ADN2817 does not output the BER at the normal
decision instant. It outputs pseudo-BER measurements to the
left and right of the normal decision instants, from which the
user must calculate what the BER is at the normal decision
instant. A microporcessor will be required to parse the data,
detecting and removing non-gaussian regions and using the
remaining data for BER extrapolation.
Secondary Mode of Operation
A secondary mode of operation is implemented. This mode is
to give easy access to a coarse estimate of the eye quality. The
circuitry is similar to that already described except that the
measurement is performed autonomously by the ADN2817,
and the result is output as a voltage on a pin, from which the
actual BER can be inferred. As this mode does not perform
scanning of the eye to separate out deterministic from random
jitter effects the method can only predict the BER to within
perhaps 2 decades, under normal applied jitter conditions.
The user merely has to bring the Automode pin low, and read
the voltage on the VBER pin, see Figure XX. Alternatively a 6
bit value can be read over the I2C. In secondary mode the
dynamic range is limited.


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