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ADN2817 Datasheet(PDF) 25 Page - Analog Devices

No. de Pieza. ADN2817
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Descarga  35 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2817 Datasheet(HTML) 25 Page - Analog Devices

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Preliminary Technical Data
ADN2817/ADN2818
Rev.Pr A | Page 25 of 35
Figure XX. VBER –vs- Bit Error Rate
Fi
LOS Configuration
The LOS detector output, LOS Pin 22, can be configured to be
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures the
LOS pin to be active low when a loss of signal condition is
detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2817/ADN2818
in the operating mode that it was previously programmed to in
registers CTRL[A], CTRL[B], and CTRL[C].
FDDI Mode
A scheme has been implemented on the ADN2817/2818 that
enables the device to lock to input data streams that appear as
sub-harmonics of the desired datarate, e.g. FDDI during link
synchronization. This works for any code where a subharmonic
down to the 31st is transmitted. FDDI uses the 5th
subharmonic. The implementation requires certain
programming by the user and more importantly certain
assumptions about the incoming data.
The user is required to program the part into FDDI mode by
setting bit FDDI_MODE[7]=1. The user then needs to program
the target datarate, (for FDDI this is 125MHz). This is done by
programming an upper and lower 9-bit code into I2C registers
HI_CODE[8..0], LO_CODE[8..0], and CODE_LSB[1..0]. See
Table XX for a look-up table showing the correct register
settings for each datarate. The user must also program the
subharmonic ratio into I2C register FDDI_MODE[6..2] that the
ADN2817/18 needs to lock on to, e.g. FDDI_MODE[6..2] =
00101 for FDDI (5th subharmonic). The user has to de-program
FDDI mode before the next datarate is applied.
Here is what is required of the incoming data:
1.
The subharmonic must be a clock-type waveform i.e.
transition density equal to 1 at the subharmonic
frequency.
2.
The subharmonic must be continued to be applied
until LOL goes LOW, i.e. until acquisition is
completed. It doesn't matter how long the
subharmonic remains after LOL goes LOW.
In FDDI Mode, the output of the ADN2817 is squelched until
the device has acquired lock of the subharmonic input. This
causes all zeros to be transmitted out of the 2817 until lock has
been achieved. Once locked, the outputs are enabled and begin
transmitting data. For FDDI protocol, this would be when the
'H' symbols are being transmitted during link synchronization.
Double Data Rate Mode
Setting I2C bit XXXX[X] = 1 puts the ADN2817/18 clock
output through divide by two circuitry allowing direct
interfacing to FPGAs that support data clocking on both rising
and falling edges.
CLK HOLDOVER MODE
CLK Holdover Mode 2A:
This mode of operation will be available in all LTD modes: The
output clock frequency will remain within +/-5% if the input
data is removed or changed. To operate in this mode, the user
would write to the I2C to put the part into CLK Holdover Mode
2A mode by setting SEL_MODE[2]=1. The user must then
initiate an acquisition via a software reset. The device will then
lock onto the input datarate. At this point the output frequency
remains within +/- 5% of the intial acquired value regardless of
whether or not the input data is taken away or the datarate
changes. Only a sw reset can initiate a new acquistion in this
mode.
CLK Holdover Mode 2B:
This mode is selected by setting SEL_MODE[1]=1. In this
mode, the output clock stays within +/-5% of the initial
acquired frequency, even if the input data is taken away. Unlike
CLK Holdover Mode 2A, in this mode the ADN2817/18 will
initiate a new frequency acquisition automatically if the input
datarate changes. This mode requires the inputs to be DC
coupled because if the inputs are AC coupled and the input is
taken away, any noise present on the inputs may be large
enough to trigger a new frequency acquisition which would
cause the clock output frequency to change.
CDR BYPASS MODE
The CDR on the ADN2817/18 can be bypassed by setting bit
CTRLD[7]=1. In this mode the ADN2817/18 will feed the input
directly through the input amplifiers to the output buffer,


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