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ADN2865 Datasheet(PDF) 4 Page - Analog Devices

No. de Pieza. ADN2865
Descripción  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES
Descarga  33 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2865 Datasheet(HTML) 4 Page - Analog Devices

 
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ADN2865
Preliminary Technical Data
Rev. PrA | Page 4 of 33
Parameter
Conditions
Min
Typ
Max
Unit
DATA RATE READBACK ACCURACY
Coarse Readback
(See Table )
10
%
Fine Readback
In addition to REFCLK accuracy
Data rate < 20 Mb/s
200
ppm
Data rate > 20 Mb/s
100
ppm
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT
300
350
mA
OPERATING TEMPERATURE RANGE
–40
+85
°C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
OC-48
2000
kHz
OC-12
500
kHz
OC-3
130
kHz
Jitter Peaking
OC-48
0
0.1
dB
OC-12
0
0.1
dB
OC-3
0
0.1
dB
Jitter Generation
OC-48, 12 kHz to 20 MHz
TBD
TBD
UI rms
TBD
0.33
UI p-p
OC-12, 12 kHz to 5 MHz
TBD
TBD
UI rms
TBD
0.2
UI p-p
OC-3, 12 kHz to 1.3 MHz
TBD
TBD
UI rms
TBD
0.2
UI p-p
Jitter Tolerance
OC-48, 223 − 1 PRBS
100 kHz
0.75
UI p-p
1 MHz
0.075
UI p-p
20 MHz
0.075
UI p-p
OC-12, 223 − 1 PRBS
25 kHz
0.75
UI p-p
250 kHzError! Bookmark not defined.
0.075
UI p-p
OC-3, 223 − 1 PRBS
6500 Hz
0.75
UI p-p
65 kHz
0.075
UI p-p
Power Supply Rejection
See Figure XX.
TBD
dB


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