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ADN2865 Datasheet(PDF) 14 Page - Analog Devices

No. de pieza ADN2865
Descripción Electrónicos  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADN2865 Datasheet(HTML) 14 Page - Analog Devices

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ADN2865
Preliminary Technical Data
Rev. PrA | Page 14 of 33
Table 8. Control Register, CTRLA1
FREF Range
Datarate/Div_FREF Ratio
Measure Datarate
Lock to Reference
D7
D6
D5
D4
D3
D2
D1
D0
0
0
12.3 MHz to 25 MHz
0
0
0
0
1
Set to 1 to measure datarate
0 = Lock to input data
0
1
25 MHz to 50 MHz
0
0
0
1
2
1 = Lock to reference clock
1
0
50 MHz to 100 MHz
0
0
1
0
4
1
1
100 MHz to 200 MHz
n
2n
1
0
0
0
256
1 Where DIV_F
REF
is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
Reset MISC[2]
D7
D6
D5
D4
D3
D2
D1
D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by
0 to reset ADN2865
Set
to 0
Write a 1 followed by
0 to reset MISC[2]
Set
to 0
Set
to 0
Set
to 0
Table 10. Control Register, CTRLC
Signal Degrade Threshold
Signal Degrade Mode
Config LOS
SERCLK
D7
D6
D5
D4
D3
D2
D1
D0
0 = Active high LOS
0 = Power Down
SERCLK buffer
Set
to 0
Set
to 0
Set
to 0
0=Set SD Threshold to 9mV
1=Set SD Threshold to 1.9x
LOS Threshold
0= Disable Signal Degrade
Mode
1= Enable Signal Degrade
Mode
Set
to 0
1 = Active low LOS
1 = Enable SERCLK
buffer
Table 11. Control Register, CTRLD
CDR Bypass
Buffer Control
Initiate PRBS
PRBS Mode
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Power Down
0=CDR Enabled
1=CDR Disabled
0=Normal
operation
1=Power Down
LVDS drivers
0=Normal
operation
1=Power Down
CML drivers
0
Write a 1 followed by 0
to initiate PRBS
Generate Sequence
0
0
0
1
1
0
Generate Mode
Detect Mode,
compares errors
Table 12. Control Register, CTRLE
RXCLK Alignment to RXDATA
Tx Mode
Bus Reversal
D7
D6
D5
D4
D3
D2
D1
D0
0=Enable align
1=Disable align
RXDATA[7:0]
0=Bit 0 is last received
TXDATA[7:0]
0=Bit 0 is last sent
Set
To 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
+1 UI
0
-3 UI
+4 UI
+2 UI
+4 UI
-2 UI
0=Sync Mode
1=Align
1=Bit 7 is last received
1=Bit 7 is last sent


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