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ADN2865 Datasheet(PDF) 20 Page - Analog Devices |
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ADN2865 Datasheet(HTML) 20 Page - Analog Devices |
20 / 33 page ADN2865 Preliminary Technical Data Rev. PrA | Page 20 of 33 FUNCTIONAL DESCRIPTION SERDES The ADN2865 has an integrated serializer / deserializer and clock divider which allows the continuous rate CDR to interface directly to an FPGA or digital ASIC, such a s a Media Access Controller (MAC), resulting in power and space savings. The recovered clock is divided by 16 and is used to transfer 8 bits of receive data to the MAC on both the rising and falling edge. Both RXCLKP/N and RXDATAP/N[7:0] use LVDS signaling for noise reasons and have a relative phase which is adjustable via the I2C interface, per table 12 on page 14. Half rate (1.25Gb/s) transmit data can also be serialised by the ADN2865 at the CML output using the recovered clock from the receive channel. An optional CML clock output is available. The parallel interface consists of 8 LVCMOS / LVTTL inputs with an optional TXCLK at the divde by 8 rate. Two timing modes are available, sync mode and align mode. Sync Mode This is the default mode of operation. and does not require a TXCLK signal. Instead, TXDATA[7:0] is timed from RXCLK and the round trip delay between these signals must meet the setup and hold time requirement specified in table 3 to avoid corrupting the serial bit stream. Sync mode is useful in applications which require a stable timing relationship between the input and output serial bit streams. Align Mode This mode is controlled using the I2C interface and requires the use of TXCLK which is used to latch TXDATA internally. When enabled, align mode centers this latched data with respect to the internal divide by 8 sampling clock, which can render the interface less sensitive to variation in the timing of TXDATA[7:0] relative to RXCLK. In a typical application, the propagation delay between RXCLK and TXDATA[7:0] will vary with process, temperature and supply voltage through the external MAC device. This variation can be calibrated out by enabling and then disabling align mode. The downside to using align mode is that the calibration process leads to additional uncertainty in the serial bit timing relative to the input bit stream by +/- 1 UI. In align mode, it is necessary to meet the setup and hold time for TXDATA[7:0] relative to TXCLK. Bit order reversal is supported for both the receive and transmit parallel buses using the I2C interface. EDGE DETECTOR RESET COUNTER TXDATA[7:0] TXCLK REGISTER SERIALISER REGISTER ALIGN MODE DIVIDE BY 8 Dn+1[7:0] Dn[7:0] TXCLK DIV BY 8 Figure 21. Align Mode Operation FREQUENCY ACQUISITION The ADN2865 acquires frequency from the data over a range of data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle. The VCO frequency is reset to the bottom of its range, which is 12.3 MHz. The frequency detector then compares this VCO frequency and the incoming data frequency and increments the VCO frequency, if necessary. Initially, the VCO frequency is incremented in large steps to aid fast acquisi- tion. As the VCO frequency approaches the data frequency, the step size is reduced until the VCO frequency is within 250 ppm of the data frequency, at which point LOL is de-asserted. Once LOL is de-asserted, the frequency-locked loop is turned off. The PLL/DLL pulls in the VCO frequency the rest of the way until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pins 14 and 15. A 0.47 μF ± 20%, X7R ceramic chip capacitor with < 10 nA leakage current is recommended. Leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 μF capacitor, ~3 V, by the insulation resistance of the capacitor. The insulation resistance of the 0.47 uF capacitor should be greater than 300 MΩ LOCK DETECTOR OPERATION The lock detector on the ADN2865 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2865 is a continuous rate CDR that locks onto any data rate from 12.3 Mb/s to 2.7 Gb/s without the use of a reference clock as an acquisition aid. In this mode, the lock detector monitors the frequency difference between the VCO and the input data frequency, and de-asserts the loss of lock signal, which appears on LOL Pin 30, when the VCO is |
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