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ADN2865 Datasheet(PDF) 24 Page - Analog Devices |
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ADN2865 Datasheet(HTML) 24 Page - Analog Devices |
24 / 33 page ADN2865 Preliminary Technical Data Rev. PrA | Page 24 of 33 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2865 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Table 16. CTRLA Settings CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio 00 12.3 to 25 0000 1 01 25 to 50 0001 2 10 50 to 100 n 2n 11 100 to 200 1000 256 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF, where DIV_FREF represents the divided-down reference referred to the 12.3 MHz to 25 MHz band. For example, if the reference clock frequency was 38.88 MHz and the input data rate was 622.08 Mb/s, then CTRLA[7:6] would be set to [01] to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] would be set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 25 In this mode, if the ADN2865 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2865 is operating in lock to reference mode, if the user ever changes the reference frequency, the FREF range (CTRLA[7:6]), or the FREF ratio (CTRLA[5:2]), this must be followed by writing a 0 to 1 transition into the CTRLA[0] bit to initiate a new lock to reference command. Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2865 compares the frequency of the incoming data to the incoming reference clock and returns a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy of the ADN2865 data rate measurement. For example, if a 100-ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. The reference clock can range from 12.3 MHz and 200 MHz. The ADN2865 expects a reference clock between 12.3 MHz and 25 MHz by default. If it is between 25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2865 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2865. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. Step 2: Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Step 3: Read back MISC[2]. If it is 0, then the measurement is not complete. If it is 1, then the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. Step 4: Read back the data rate from registers FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0]. Use the following equation to determine the data rate: [] ( ) ) _ 14 ( 2 / 0 .. 22 RATE SEL REFCLK DATARATE f FREQ f + × = where: FREQ[22:0] is the reading from FREQ2[6:0] (MSByte), FREQ1[7:0], and FREQ0[7:0] (LSByte). Table 17. D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0 FREQ2[6:0] FREQ1[7:0] FREQ0[7:0] fDATARATE is the data rate (Mb/s). fREFCLK is the REFCLK frequency (MHz). SEL_RATE is the setting from CTRLA[7:6]. For example, if the reference clock frequency is 32 MHz, SEL_RATE = 1, since the CTRLA[7:6] setting would be [01], because the reference frequency would fall into the 25 MHz to 50 MHz range. Assume for this example that the input data rate is 2.488 Gb/s (OC-48). After following Steps 1 through 4, the value that is read back on FREQ[22:0] = 0x26E010, which is equal to 2.5477 × 106. Plugging this value into the equation yields ( ) ( ) Gb/s 488 . 2 2 / 6 e 32 6 e 5477 . 2 ) 1 14 ( = × + If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measurement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Steps 2 through 4 to read back the new data rate. Note: A data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid. |
Número de pieza similar - ADN2865 |
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Descripción similar - ADN2865 |
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