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ADN2865 Datasheet(PDF) 25 Page - Analog Devices |
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ADN2865 Datasheet(HTML) 25 Page - Analog Devices |
25 / 33 page Preliminary Technical Data ADN2865 Rev. PrA | Page 25 of 33 Additional Features Available via the I2C Interface Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately +10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is de-asserted. The 8 MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table provides coarse data rate readback to within ±10%. Fi LOS Configuration The LOS detector output, LOS Pin 22, can be configured to be either active high or active low. If CTRLC[2] is set to Logic 0 (default), the LOS pin is active high when a loss of signal condition is detected. Writing a 1 to CTRLC[2] configures the LOS pin to be active low when a loss of signal condition is detected. System Reset A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2865 in the operating mode that it was previously programmed to in registers CTRL[A], CTRL[B], and CTRL[C]. FDDI Mode A scheme has been implemented on the ADN2865 that enables the device to lock to input data streams that appear as sub- harmonics of the desired datarate, e.g. FDDI during link synchronization. This works for any code where a subharmonic down to the 31st is transmitted. FDDI uses the 5th subharmonic. The implementation requires certain programming by the user and more importantly certain assumptions about the incoming data. The user is required to program the part into FDDI mode by setting bit FDDI_MODE[7]=1. The user then needs to program the target datarate, (for FDDI this is 125MHz). This is done by programming an upper and lower 9-bit code into I2C registers HI_CODE[8..0], LO_CODE[8..0], and CODE_LSB[1..0]. See Table XX for a look-up table showing the correct register settings for each datarate. The user must also program the subharmonic ratio into I2C register FDDI_MODE[6..2] that the ADN2865 needs to lock on to, e.g. FDDI_MODE[6..2] = 00101 for FDDI (5th subharmonic). The user has to de-program FDDI mode before the next datarate is applied. Here is what is required of the incoming data: 1. The subharmonic must be a clock-type waveform i.e. transition density equal to 1 at the subharmonic frequency. 2. The subharmonic must be continued to be applied until LOL goes LOW, i.e. until acquisition is completed. It doesn't matter how long the subharmonic remains after LOL goes LOW. In FDDI Mode, the output of the ADN2865 is squelched until the device has acquired lock of the subharmonic input. This causes all zeros to be transmitted out of the 2865 until lock has been achieved. Once locked, the outputs are enabled and begin transmitting data. For FDDI protocol, this would be when the 'H' symbols are being transmitted during link synchronization. CLK HOLDOVER MODE CLK Holdover Mode 2A: This mode of operation will be available in all LTD modes: The output clock frequency will remain within +/-5% if the input data is removed or changed. To operate in this mode, the user would write to the I2C to put the part into CLK Holdover Mode 2A mode by setting SEL_MODE[2]=1. The user must then initiate an acquisition via a software reset. The device will then lock onto the input datarate. At this point the output frequency remains within +/- 5% of the intial acquired value regardless of whether or not the input data is taken away or the datarate changes. Only a sw reset can initiate a new acquistion in this mode. CLK Holdover Mode 2B: This mode is selected by setting SEL_MODE[1]=1. In this mode, the output clock stays within +/-5% of the initial acquired frequency, even if the input data is taken away. Unlike CLK Holdover Mode 2A, in this mode the ADN2865 will initiate a new frequency acquisition automatically if the input datarate changes. This mode requires the inputs to be DC coupled because if the inputs are AC coupled and the input is taken away, any noise present on the inputs may be large enough to trigger a new frequency acquisition which would cause the clock output frequency to change. CDR BYPASS MODE The CDR on the ADN2865 can be bypassed by setting bit CTRLD[7]=1. In this mode the ADN2865 will feed the input directly through the input amplifiers to the output buffer, completely bypassing the CDR. DISABLE OUTPUT BUFFERS The ADN2865 provides the option of disabling the output buffers for power savings. The LVDS output buffers can be disabled by setting CTRLD[6]=1. For additional power savings, e.g. in a low power standby mode, the CML output buffers can also be disabled by setting CTRLD[5]=1. |
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Descripción similar - ADN2865 |
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