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ADN2865 Datasheet(PDF) 26 Page - Analog Devices |
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ADN2865 Datasheet(HTML) 26 Page - Analog Devices |
26 / 33 page ADN2865 Preliminary Technical Data Rev. PrA | Page 26 of 33 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. The exposed pad should be connected to the GND plane using plugged vias so that solder does not leak through the vias during reflow. Use of a 10 μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2865 VCC pins. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pins 7,45 & 50, which supplies power to the high speed LVDS & CML output buffers. Refer to the schematic in Figure for recommended connections. By using adjacent power supply and GND planes, excellent high frequency decoupling can be realized by using close spacing between the planes. This capacitance is given by ( ) pF ε 88 . 0 A/d C r plane = where: ε r is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/ Figure 27. Typical ADN2865 Applications Circuit |
Número de pieza similar - ADN2865 |
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Descripción similar - ADN2865 |
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