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NB6L611 Datasheet(PDF) 1 Page - ON Semiconductor

No. de Pieza. NB6L611
Descripción  2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
Descarga  9 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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NB6L611 Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
1
Publication Order Number:
NB6L611/D
NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
Multi−Level Inputs with Internal Termination
Description
The NB6L611 is a differential 1:2 fanout buffer. The differential
inputs incorporate internal 50
W termination resistors that are accessed
through the VTD pins and will accept LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels.
The VREFAC pin is an internally generated voltage supply available
to this device only. VREFAC is used as a reference voltage for
single−ended PECL or NECL inputs. For all single−ended input
conditions, the unused complementary differential input is connected
to VREFAC as a switching reference voltage. VREFAC may also rebias
capacitor−coupled inputs. When used, decouple VREFAC with a
0.01
mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VREFAC output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAX
™ family of high
performance clock products.
Features
Maximum Input Clock Frequency > 4.0 GHz, Typical
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V
NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output Voltage
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
MARKING
DIAGRAM*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
NB6L
611
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
16
1
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
D
D
VTD
VTD


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