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ADP1864 Datasheet(PDF) 5 Page - Analog Devices

No. de Pieza. ADP1864
Descripción  Constant Frequency Current-Mode Step-Down DC/DC Controller in TSOT
Descarga  16 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADP1864 Datasheet(HTML) 5 Page - Analog Devices

 
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ADP1864
Rev. 0 | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1864
TOP VIEW
(Not to Scale)
COMP
1
GND
2
FB
3
IN
PGATE
6
5
CS
4
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a
series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between
COMP and GND to further reduce switching jitter. The value of this is typically one tenth of the main
compensation capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET.
2
GND
Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small
analog GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to
the GND pin. See the Layout Considerations section for more information.
3
FB
Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The
regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin.
4
CS
Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal
used to terminate the PWM on-time. Place a current sense resistor between IN and CS to set the current limit. The
current limit threshold is typically 125 mV.
5
IN
Power Input. IN is the ADP1864 power supply and the positive input of the current sense amplifier. Connect IN
to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor, as close as
possible to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the
IN pin.
6
PGATE
Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the
external MOSFET.


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