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ADSST-EM-3035

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ARCHITECTURE OVERVIEW

The ADSST-2185KST-133 instruction set provides flexible

data moves and multifunction (one or two data moves with a

computation) instructions. Every instruction can be executed in

a single processor cycle. The ADSST-2185KST-133 assembly

language uses an algebraic syntax for ease of coding and read-

ability. A comprehensive set of development tools supports

program development.

Figure 1 is an overall block diagram of the ADSST-2185KST-133.

The processor contains three independent computational units:

the ALU, the multiplier/accumulator (MAC), and the shifter.

The computational units process 16-bit data directly and have

provisions to support multiprecision computations. The ALU

performs a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with 40

bits of accumulation. The shifter performs logical and arithmetic

shifts, normalization, denormalization and derive exponent

operations.

The shifter can be used to efficiently implement numeric format

control including multiword and block floating-point representations.

The internal result (R) bus connects the computational units

so the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these com-

putational units. The sequencer supports conditional jumps,

subroutine calls, and returns in a single cycle. With internal loop

counters and loop stacks, the ADSST-2185KST-133 executes

looped code with zero overhead. No explicit jump instructions

are required to maintain loops.

Two data address generators (DAGs) provide addresses for simul-

taneous dual operand fetches from data memory and program memory.

Each DAG maintains and updates four address pointers. Whenever

the pointer is used to access data (indirect addressing), it is post-

modified by the value of one of four possible modify registers. A

length value may be associated with each pointer to implement

automatic modulo addressing for circular buffers.

Efficient data transfer is achieved with the use of five internal buses:

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the two

data buses (PMD and DMD) share a single external data bus. Byte

memory space and I/O memory space also share the external buses.

Program memory can store both instructions and data, permitting

the ADSST-2185KST-133 to fetch two operands in a single cycle,

one from program memory and one from data memory. The

ADSST-2185KST-133 can fetch an operand from program

memory and the next instruction in the same cycle.

When configured in host mode, the ADSST-2185KST-133 has

a 16-bit Internal DMA port (IDMA port) for connection to

external systems. The IDMA port is made up of 16 data/address

pins and five control pins. The IDMA port provides transparent,

direct access to the DSP’s on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with programmable

wait state generation. External devices can gain control of external

buses with bus request/grant signals (

BR, BGH, and BG). One

execution mode (Go Mode) allows the ADSST-2185KST-133

to continue running from on-chip memory. Normal execution

mode requires the processor to halt while buses are granted.

The ADSST-2185KST-133 can respond to 11 interrupts.

There are up to six external interrupts (one edge-sensitive, two

level-sensitive, and three configurable) and seven internal inter-

rupts generated by the timer, the serial ports (SPORTs), the

Byte DMA port, and the power-down circuitry. There is also a

master

RESET signal. The two serial ports provide a complete

synchronous serial interface with optional companding in hard-

ware and a wide variety of framed or frameless data transmit

and receive modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

The ADSST-2185KST-133 provides up to 13 general purpose

flag pins. The data input and output pins on SPORT1 can be

alternatively configured as an input flag and an output flag. In

addition, eight flags are programmable as inputs or outputs, and

three flags are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) decrements every n processor

cycle, where n is a scaling value stored in an 8-bit register (TSCALE).

When the value of the count register reaches zero, an interrupt is

generated and the count register is reloaded from a 16-bit period

register (TPERIOD).

Serial Ports

The ADSST-2185KST-133 incorporates two complete synchronous

serial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Here is a brief list of the capabilities of the ADSST-2185KST-133

SPORTs. For additional information on Serial Ports, refer to

the ADSP-2100 Family User’s Manual, Third Edition.

transmit and receive section.

serial clock internally.

sections. Sections run in a frameless mode or with frame synchro-

nization signals internally or externally generated. Frame

sync signals are active high or inverted, with either of two

pulsewidths and timings.

provide optional A-law and M-law companding according to

CCITT recommendation G.711.

interrupts on completing a data-word transfer.

data with only one overhead cycle per data-word. An interrupt

is generated after a data buffer transfer.