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ADSST-EM-3035K Datasheet(PDF) 2 Page - Analog Devices |
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ADSST-EM-3035K Datasheet(HTML) 2 Page - Analog Devices |
2 / 20 page REV. 0 ADSST-EM-3035 –2– ADSST-2185KST-133 (DSP) SPECIFICATION FEATURES 30 ns Instruction Cycle 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch Three-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode ADSP-2100 Family Code Compatible, with Instruction Set Extensions 40 kBytes of On-Chip RAM, Configured as 8 KWords On-Chip Program Memory RAM and 8 KWords On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP 16-Bit Internal DMA Port for High Speed Access to On- Chip Memory (Mode Selectable) 4 MBytes Byte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits Glueless System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION The ADSST-2185KST-133 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSST-2185KST-133 combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSST-2185KST-133 integrates 40 kBytes of on-chip memory configured as 8 Kwords (24-bit) of program RAM and 8 Kwords (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSST-2185KST-133 is available in a 100-lead TQFP package. In addition, the ADSST-2185KST-133 supports instructions that include bit manipulations, bit set, bit clear, bit toggle, bit test new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory trans- fers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSST-2185KST-133 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSST-2185KST-133’s flexible architecture and com- prehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSST-2185KST-133 can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation • This takes place while the processor continues to: Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer SERIAL PORTS SPORT 1 SPORT0 MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER 16K 24 PROGRAM MEMORY 16K 16 DATA MEMORY TIMER ADSP-2100 BASE ARCHITECTURE SHIFTER MAC ALU ARITHMETIC UNITS POWER-DOWN CONTROL PROGRAM SEQUENCER DAG 2 DAG 1 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS INTERNAL DMA PORT EXTERNAL DATA BUS OR FULL MEMORY MODE HOST MODE Figure 1. Functional Block Diagram |
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