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ADUM3100ARZ Datasheet(PDF) 4 Page - Analog Devices |
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ADUM3100ARZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 16 page ADuM3100 Rev. A | Page 4 of 16 ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION1 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent IDD1 (Q) 0.7 0.9 mA VI = 0 V or VDD1 Output Supply Current, Quiescent IDD2 (Q) 0.1 0.2 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) (See Figure 4) IDD1 (25) 2.6 3.4 mA 12.5 MHz logic signal freq. Output Supply Current2 (25 Mbps) (See Figure 5) IDD2 (25) 0.4 0.8 mA 12.5 MHz logic signal freq. Input Supply Current (50 Mbps) (See Figure 4) IDD1 (50) 4.6 6.6 mA 25 MHz logic signal freq., ADuM3100BR only Output Supply Current2 (50 Mbps) (See Figure 5) IDD2 (50) 0.7 1.7 mA 25 MHz logic signal freq., ADuM3100BR only Input Current II –10 +0.01 +10 μA 0 ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 – 0.1 3.3 V IO = –20 μA, VI = VIH VDD2 – 0.5 3.0 V IO = –2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 0.04 0.1 V IO = 400 μA, VI = VIL 0.3 0.4 V IO = 2.5 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM3100AR Minimum Pulse Width3 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 25 Mbps CL = 15 pF, CMOS signal levels For ADuM3100BR Minimum Pulse Width3 PW 10 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 50 100 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low Output5, 6 (See Figure 7) tPHL 14.5 28 ns CL = 15 pF, CMOS signal levels Propagation Delay Time to Logic High Output5, 6 (See Figure 7) tPLH 15.0 28 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion |tPLH − tPHL|6 PWD 0.5 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature7 10 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature)6,8 tPSK1 15 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature, Supplies)6, 8 tPSK2 12 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output9 |CML|, |CMH| 25 35 kV/μs VI = 0 or VDD1, VCM = 1000 V, transient magnitude = 800 V Input Dynamic Supply Current10 IDDI (D) 0.08 mA/Mbps Output Dynamic Supply Current10 IDDO (D) 0.01 mA/Mbps See notes on Page 6. |
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