Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD5664BRMZ-REEL7 Datasheet(PDF) 5 Page - Analog Devices |
|
AD5664BRMZ-REEL7 Datasheet(HTML) 5 Page - Analog Devices |
5 / 24 page AD5624/AD5664 Rev. 0 | Page 5 of 24 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter1 VDD = 2.7 V to 5.5 V Unit Conditions/Comments t12 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 13 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to SCLK fall ignore t10 0 ns min SCLK falling edge to SYNC fall ignore 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM DB0 DB23 t10 SCLK SYNC DIN t1 t9 t7 t2 t3 t6 t5 t4 t8 Figure 2. Serial Write Operation |
Número de pieza similar - AD5664BRMZ-REEL7 |
|
Descripción similar - AD5664BRMZ-REEL7 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |