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AD5666ARUZ-2REEL7 Datasheet(PDF) 8 Page - Analog Devices |
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AD5666ARUZ-2REEL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 28 page AD5666 Rev. A | Page 8 of 28 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments t11 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 13 ns min SYNC to SCLK falling edge set-up time t5 4 ns min Data set-up time t6 4 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to SCLK fall ignore t10 0 ns min SCLK falling edge to SYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min SCLK falling edge to LDAC rising edge t13 5 ns min CLR pulse width low t14 0 ns min SCLK falling edge to LDAC falling edge t15 300 ns typ CLR pulse activation time t162, 3 22 ns max SCLK rising edge to SDO valid t173 5 ns min SCLK falling edge to SYNC rising edge t183 8 ns min SYNC rising edge to SCLK rising edge t193 0 ns min SYNC rising edge to LDAC falling edge 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 2 Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode. 3 Daisy-chain mode only. 2mA IOL 2mA IOH VOH (MIN) TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications |
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