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NCP4330 Datasheet(PDF) 2 Page - ON Semiconductor

No. de Pieza. NCP4330
Descripción  Post Regulation Driver
Descarga  18 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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NCP4330 Datasheet(HTML) 2 Page - ON Semiconductor

 
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2
Figure 2. Timing Diagram(s)
Converter Winding
Voltage
C_ramp Voltage
High−Side Driver
Low−Side Driver
100 ns delay
VrefH
Time
(referenced to
HS MOSFET source)
Time
Time
Time
0 V
0 V
VrefL
Time
Synchronization
Signal
Time
Internal RESET
Signal
100 ns delay
2.55 V
DETAILED PIN DESCRIPTION(S)
Pin
Number
Name
Function
1
HS_DRV
“HS_DRV” is the gate driver of the high−side MOSFET.
2
BST
“BST” is the bootstrap pin. A 0.1
mF to 1.0 mF ceramic capacitor should be connected between this pin
and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the high−side
driver (“HS_DRV”).
3
RST
The “RST” pin resets the C_ramp voltage in order to synchronize the post−regulator free−wheeling
sequence to the forward converter demagnetization phase.
4
C_ramp
The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the high−side
MOSFET (in conjunction with “I_ramp” current).
5
I_ramp
The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after
which the high−side MOSFET is turned on. By this way, it modules the high−side MOSFET on time in
order to regulate the output voltage.
6
VDD
“VDD” is the power supply input. A 0.1 mF to 1.0 mF ceramic capacitor should be connected from this pin
to ground for decoupling.
7
LS_DRV
“LS_DRV” is the driver output of the low−side MOSFET gate.
8
GND
Ground.


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