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Z86E72 Datasheet(PDF) 70 Page - Zilog, Inc.

No. de Pieza. Z86E72
Descripción  OTP IR MICROCONTROLLERS
Descarga  74 Pages
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Fabricante  ZILOG [Zilog, Inc.]
Página de inicio  http://www.zilog.com
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Z86E72 Datasheet(HTML) 70 Page - Zilog, Inc.

 
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Z86E72/E73
OTP IR Microcontrollers
1-70
P R E L I M I N A R Y
DS96LVO1100
Z8® STANDARD CONTROL REGISTER DIAGRAMS (Continued)
Figure 61. Interrupt Priority Registers
((0) F9H: Write Only)
Figure 62. Interrupt Request Register
((0) FAH: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0)
R249 IPR
D7
D6
D5
D4
D3
D2
D1
D0
R250 IRQ
Inter Edge
P31
↓ P32 ↓ = 00
P31
↓ P32 ↑ = 01
P31
↑ P32 ↓ = 10
P31
↑↓ P32 ↑↓ = 11
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
Reserved (Must be 0)
Default Setting After Reset = 0000 0000
Figure 63. Interrupt Mask Register
((0) FBH: Read/Write)
Figure 64. Flag Register
((0) FCH: Read/Write
Figure 65. Register Pointer
((0) FDH: Read/Write)
D7 D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0)
1 Enables IRQ4-IRQ0
(D0 = IRQ0)
0 Master Interrupt Disable*
1 Master Interrupt Enable
R251 IMR
* Default Setting After Reset
Reserved (Must be 0)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Tag
Sign Flag
Zero Flag
Carry Flag
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register (Bank)
Pointer
Working Register
Pointer
R253 RP
Default Setting After
Reset = 0000


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