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Z86E72 Datasheet(PDF) 14 Page - Zilog, Inc.

No. de Pieza. Z86E72
Descripción  OTP IR MICROCONTROLLERS
Descarga  74 Pages
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Fabricante  ZILOG [Zilog, Inc.]
Página de inicio  http://www.zilog.com
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Z86E72 Datasheet(HTML) 14 Page - Zilog, Inc.

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Z86E72/E73
OTP IR Microcontrollers
1-14
P R E L I M I N A R Y
DS96LVO1100
AC CHARACTERISTICS
Preliminary
External I/O or Memory Read and Write Timing Table
TA = 0°C to +70°C
16 MHz
No. Symbol
Parameter
VCC
Min.
Max.
Units
Notes
1
TdA(AS)
Address Valid to
/AS Rising Delay
3.0V
5.5V
55
55
ns
ns
2
2
TdAS(A)
/AS Rising to Address Float Delay
3.0V
5.5V
70
70
ns
ns
2
3
TdAS(DR)
/AS Rising to Read Data Required Valid
3.0V
5.5V
400
400
ns
ns
1,2
1,2
4
TwAS
/AS Low Width
3.0V
5.5V
80
80
ns
ns
2
2
5
Td
Address Float to
/DS Falling
3.0V
5.5V
0
0
ns
ns
6
TwDSR
/DS (Read) Low Width
3.0V
5.5V
300
300
ns
ns
1,2
7
TwDSW
/DS (Write) Low Width
3.0V
5.5V
165
165
ns
ns
1,2
8
TdDSR(DR)
/DS Falling to Read Data Required Valid
3.0V
5.5V
260
260
ns
ns
1,2
9
ThDR(DS)
Read Data to
/DS Rising Hold Time
3.0V
5.5V
0
0
ns
ns
10
TdDS(A)
/DS Rising to Address Active Delay
3.0V
5.5V
85
95
ns
ns
2
11
TdDS(AS)
/DS Rising to /AS
Falling Delay
3.0V
5.5V
60
70
ns
ns
2
12
TdR/W(AS)
R//W Valid to /AS
Rising Delay
3.0V
5.5V
70
70
ns
ns
2
13
TdDS(R/W)
/DS Rising to
R//W Not Valid
3.0V
5.5V
70
70
ns
ns
2
14
TdDW(DSW) Write Data Valid to /DS Falling (Write)
Delay
3.0V
5.5V
80
80
ns
ns
2
15
TdDS(DW)
/DS Rising to Write
Data Not Valid Delay
3.0V
5.5V
70
80
ns
ns
2
16
TdA(DR)
Address Valid to Read Data Required
Valid
3.0V
5.5V
475
475
ns
ns
1,2
17
TdAS(DS)
/AS Rising to
/DS Falling Delay
3.0V
5.5V
100
100
ns
ns
2
2
18
TdDM(AS)
/DM Valid to /AS
Falling Delay
3.0V
5.5V
55
55
ns
ns
2
19
TdDS(DM)
/DS Rise to
/DM Valid Delay
3.0V
5.5V
70
70
ns
ns
20
ThDS(A)
/DS Rise to Address Valid Hold Time
3.0V
5.5V
70
70
ns
ns
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.


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