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Z86E72 Datasheet(PDF) 35 Page - Zilog, Inc.

No. de Pieza. Z86E72
Descripción  OTP IR MICROCONTROLLERS
Descarga  74 Pages
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Fabricante  ZILOG [Zilog, Inc.]
Página de inicio  http://www.zilog.com
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Z86E72 Datasheet(HTML) 35 Page - Zilog, Inc.

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Z86E72/E73
OTP IR Microcontrollers
DS96LVO1100
P R E L I M I N A R Y
1-35
1
CTR2 (D)%02: Counter/Timer16 Control Register.
CTR2 Description
T16_Enable. This field enables T16 when set to 1.
Single/Modulo-N. In Transmit Mode, when set to 0, the
counter reloads the initial value when terminal count is
reached. When set to 1, the counter stops when the termi-
nal count is reached.
In Demodulation Mode, when set to 0 , T16 captures and
reloads on detection of all the edges; when set to 1, T16
captures and detects on the first edge, but ignores the sub-
sequent edges. For details, see the description of T16 De-
modulation Mode.
Time_Out. This bit is set when T16 times out (terminal
count reached). In order to reset it, a 1 should be written to
this location.
T16_Clock. Defines the frequency of the input signal to
Counter/Timer16.
Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into LO16 and HI16.
Counter_INT_Mask. Set this bit to allow interrupt when
T16 times out.
P35_Out. This bit defines whether P35 is used as a normal
output pin or T16 output.
Field
Bit Position
Value
Description
T16_Enable
7-------
R
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Submode/Modulo-N
-6------
R/W
0
1
0
1
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize Edge
Time_Out
--5-----
R
W
0
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
T16 _Clock
---43---
R/W
00
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask
-----2--
R/W
0
1
Disable Data Capture Int.
Enable Data Capture Int.
Counter_INT_Mask
------1-
R/W
0
1
Disable Time-Out Int.
Enable Time-Out Int.
P35_Out
-------0
R/W
0*
1
P35 as Port Output
T16 Output on P35
Note: * Indicates the value upon Power-On Reset.


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