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Z86E72 Datasheet(PDF) 53 Page - Zilog, Inc.

No. de Pieza. Z86E72
Descripción  OTP IR MICROCONTROLLERS
Descarga  74 Pages
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Fabricante  ZILOG [Zilog, Inc.]
Página de inicio  http://www.zilog.com
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Z86E72 Datasheet(HTML) 53 Page - Zilog, Inc.

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Z86E72/E73
OTP IR Microcontrollers
DS96LVO1100
P R E L I M I N A R Y
1-53
1
WDT Time Select (D0, D1). Selects the WDT time period.
It is configured as shown in Table 13.
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Since the
XTAL clock is stopped during STOP mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0, which selects the RC oscillator.
Figure 43. Watch-Dog Timer Mode Register
(Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (0F) FH
WDT TAP
INT RC OSC External Clock
00
5 ms
256 TpC
01
10 ms
512 TpC
10
20 ms
1024 TpC
11
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
*
*
*
*
Table 9. WDT Time Select
D1
D0
Time-Out of
Internal RC
OSC
Time-Out of
XTAL Clock
0
0
5 ms min
256 TpC
0
1
10 ms mi
512 TpC
1
0
20 ms mi
1024 TpC
1
1
80 ms mi
4096 TpC
Notes:
TpC = XTAL clock cycle
The default on reset is 10 ms


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