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LPC3180 Datasheet(PDF) 1 Page - NXP Semiconductors

No. de Pieza. LPC3180
Descripción  16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface
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Fabricante  PHILIPS [NXP Semiconductors]
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LPC3180 Datasheet(HTML) 1 Page - NXP Semiconductors

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General description
The LPC3180 is an ARM9-based microcontroller for embedded applications requiring
high performance combined with low power dissipation. It achieves these objectives
through the combination of Philips' state-of-the-art 90 nanometer technology with an
ARM926EJ-S CPU core with a Vector Floating Point (VFP) coprocessor and a large array
of standard peripherals including USB On-The-Go.
The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per
ARM Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard
architecture with separate 32 kB instruction and data caches, a demand paged MMU,
DSP instruction extensions with a single cycle MAC, and Jazelle Java bytecode execution
hardware. A block diagram of the microcontroller is shown in Figure 1.
Power optimization in this microcontroller is done through process and technology
development (Intrinsic Power), and architectural means (Managed Power).
The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0
full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI ports, a Secure Digital
(SD) interface, and a 10-bit ADC in addition to many other features.
2.1 Key features
I ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, running
at up to 208 MHz.
I 64 kB of SRAM.
I High-performance multi-layer AHB bus system provides a separate bus for CPU data
and instruction fetch, two data buses for the DMA controller, and another for the USB
I External memory interfaces: one supports DDR and SDR SDRAM, another supports
single-level and multi-level NAND flash devices and can serve as an 8-bit parallel
I General purpose DMA controller that can be used with the SD card and SPI interfaces,
as well as for memory-to-memory transfers.
I USB 2.0 full-speed device, host (OHCI compliant), and OTG block. A dedicated PLL
provides the 48 MHz USB clock.
I Multiple serial interfaces, including seven UARTs, two SPI controllers, and two single
master I2C-bus interfaces.
I SD memory card interface.
16/32-bit ARM microcontroller; hardware floating-point
coprocessor, USB On-The-Go, and SDRAM memory interface
Rev. 01 — 2 June 2006
Preliminary data sheet

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